Anatomy of a memory access, interactivelyMemory access

28 September 2026, the routes as measured 29 September (replies y first) · every number is a fact with a source: a repository file and field, a manual page, or an RTL line · the facts: the table below, built in the repository's docs/reports/data/2026-09-28-memory-levels · a companion to Anatomy of a memory access · part of the ET-SoC-1 measurement reports

One memory access on Esperanto's ET-SoC-1, level by level, from the part that serves it down to the transistors that switch. Each level has its own diagram: the L1 data cache inside a minion, the L2 in the shire cache, the L3 across the mesh, the scratchpad, and the LPDDR4X DRAM. Every part says whether what it shows is documented for this chip (a specification, the RTL or a measurement on the lab's cards), a generic textbook circuit drawn as an illustration, or unknown, in which case it names the ask that would settle it.

How to use it

• Levels: the tabs above the drawing, or the keys 1 to 5 (L1, L2, L3, scratchpad, DRAM). The camera travels between levels, so the new level is always seen inside the old one, or the old inside the new: out of the minion into its shire (the L2), out of the shire into the chip (the L3, the scratchpad and the DRAM draw the same map and cross-fade over it), and back in. While the drawing's labels are too small or too large to read, a small label at its top left names the scales on the way, the one the camera is at in bold. The tab of the level shown, while zoomed in, goes back out to its top. The address bar keeps the view (#l2, #l1/dcache, #l1/load-hit/4, #l2/load-hit/9/cell), so a link opens the same view.
• Click any part (or Tab to it and press Space) for what it is, its numbers with their units and card coverage, and its facts with their sources; point at a number to see its source. A dashed part is unknown and its panel names the ask; a dotted part is a generic circuit.
• Zoom with the bar above the drawing, the chip diagram's: ↑ goes out one scale (from a level's top to the level outside it, the L1's minion into the L2's shire, the shire into the chip's map, and from the map on out to the package, the card, the host computer and the rack), the breadcrumb beside it goes to any scale on the way, − and + step out and in (+ into the part you picked, else the scale's usual next one), and the readout gives the size of what you see. A double click on a part, or Enter, zooms into it; Backspace zooms out. Every part leads further in: a part with a drawing of its own here opens it; any other opens the chip diagram's drawing of it, a textbook construction where the chip's own circuit is not published (each says so), and every way in ends at a transistor (TSMC's 7 nm FinFET, with its fin and channel, or the DRAM's own cell, on a DRAM process), then the silicon crystal, an atom, its nucleus, a proton and a quark. G switches the transistor's gate, or a cell's bit, between its two states. Every change of view is one smooth move, out to the scale the two views share and in again; a new address or requester that moves the part you are in goes out to where the change shows and back in.
• Accesses: the buttons beside the tabs, or [ and ]. Each access is a row of steps in the player bar above the drawing: click one on its track, or step with the Left and Right arrows (with no access chosen, the arrows glide to the neighbouring shire, bank or minion). Space pauses everything that moves, the camera included; stepping while paused shows each step's end state.
• Follow (C): the camera follows the access from scale to scale. Turn it off, or zoom yourself, and the camera stays: a step at another scale then marks its place. Dive (V): on the steps that have a circuit, the camera goes down to the transistors, plays the circuit, and comes back up.
• Tour (T) steps through this level's slides; Shift+T tours every level in order. The arrows step, Shift with an arrow jumps a slide, Q (or End tour) ends the tour; Esc does not. Present (F) goes full screen, or fills the page's frame where full screen is not allowed. P hides the panel, D switches light and dark. From the address: ?theme=light, ?panel=off, ?dive=on, ?tour=1 or ?tour=all.
• On a phone one tap on a part shows its details, with a Zoom in button under the drawing; a double tap zooms into it; a tap on a level tab zooms smoothly to that level. The drawing keeps a readable size and scrolls sideways, from its left edge; every move of the camera scrolls it too, to the part it zooms into, and ends on the new view's title (zooming in) or on the part it came from (zooming out). The example address's fields fold under fields ▾. Fit to screen, in the bar above the drawing, shows the whole level at once, in small text (the drawing zooms between the two sizes); pinching enlarges it.

SRAM or not: what each level is built from

One load, level by level

What is documented, what is generic, what is unknown

What would settle the rest: the asks

Every unknown on this page belongs to one ask. The new asks are rungs 37–44 of the hub's improvement ladder (a document to request from AI Foundry, or an experiment on the cards); the others add to a row the hub already had. The hub's §5 lists them with the rest of its asks, and each of its rows links back to the parts of these diagrams it would settle. The load these diagrams draw was measured and taken apart in Anatomy of a memory access.

Every fact on this page

The facts behind the diagrams, the panels and the captions: their level, kind, the cards they were measured on and their source. Sort by any column or filter the rows.

Related reports

• Anatomy of a memory access — one load traced from L1 to DRAM with its measured cycles and energy; this page is its companion.
• Memory hierarchy — latency, bandwidth and energy at every level.
• The ET-SoC-1, interactively — the die, a shire and a minion, and eleven data flows; this page's engine is its.
• The energy manual — what each instruction, level and message costs.
• On-chip communication — what messages cost inside a neighbourhood, a shire and across the mesh.
• Hand it to the next shire — the relay against a round trip through DRAM.
• Limits of observability — the hub: every report, what the instruments cannot see, and the asks.

Sources

Versions: published 28 September 2026; 29 September, the routes as measured (replies y first); 30 September, a smoother camera (each move one or two eased zooms) and the playback bar on top; 30 September, level tabs and taps zoom smoothly: every change of view, a level tab included, is a camera move out to the scale the two views share and in again, one tap on a phone zooms into a part, and the drawing's sideways scroll moves with the camera; 1 October, the chip diagram's Up bar, breadcrumb and readout on this page too, out from the chip's map to the package, the card and the rack, and in from every part to a transistor and its atoms (the chip diagram's scales, drawn here by the same code), a click that selects and a double click that zooms, as there.

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